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number of pins: 24 x 20 x 16 x x m -law/a-law coding: m -law x x x a-law x x gain timing rates: variable mode 64 khz to 2.048 mhz x x x x fixed mode 1.536 mhz x x 1.544 mhz x x 2.048 mhz x x x x loopback test capability x 8th-bit signaling x features table feature 29c13a 129c13a 29c14a 129c14a 29c16a 129c16a 29c17a 129c17a tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 1 post office box 655303 ? dallas, texas 75265 replace use of tcm2910a and tcm2911a in tandem with tcm2912b/c reliable silicon-gate cmos technology low power consumption: operating mod e...80 mw t ypical power-down mod e...5 mw t ypical excellent power-supply rejection ratio over frequency range of 0 hz to 50 khz no external components needed for sample, hold, and autozero functions precision internal voltage references improved version of tcm29c13 series and tcm129c13 series description the tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tcm129c14a, tcm129c16a, and tcm129c17a are single-chip pcm codecs (pulse-code-modulated encoders and decoders) and pcm line filters. these devices provide all the functions required to interface a full-duplex (4-wire) voice telephone circuit with a time-division-multiplexed (tdm) system. these devices are intended to replace the tcm2910a or tcm2911a in tandem with the tcm2912c. primary applications include: ? line interface for digital transmission and switching of t1 carrier, pabx, and central office telephone systems ? subscriber line concentrators ? digital-encryption systems ? digital voice-band data storage systems ? digital signal processing 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v bb pwro + pwro pdn dclkr pcm in fsr/tsre dgtl gnd v cc gsx anlg in anlg gnd tsx /dclkx pcm out fsx/tsxe clkr/clkx tcm29c16, tcm29c16a, tcm129c16, tcm129c17a dw or n package (top view) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v bb pwro + pwro gsr pdn clksel dclkr pcm in fsr/tsre dgtl gnd v cc gsx anlg in anlg in + anlg gnd sigx/asel tsx /dclkx pcm out fsx/tsxe clkr/clkx tcm29c13a, tcm129c13a dw or n package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v bb pwro + pwro gsr pdn clksel anlg loop sigr dclkr pcm in fsr/tsre dgtl gnd v cc gsx anlg in anlg in + anlg gnd nc sigx/asel tsx /dclkx pcm out fsx/tsxe clkx clkr tcm29c14a, tcm129c14a dw package (top view) nc no internal connection copyright ? 1996, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foa m during storage or handling to prevent electrostatic damage to the mos gates.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 2 post office box 655303 ? dallas, texas 75265 description (continued) these devices are designed to perform the transmit encoding (a/d conversion) and receive decoding (d/a conversion) as well as the transmit and receive filtering functions in a pulse-code-modulated system. they are intended to be used at the analog termination of a pcm line or trunk. the tcm29c13a, tcm29c13a, tcm29c16a, tcm29c17a, tcm129c13a, tcm129c14a, tcm129c16a, and tcm129c17a provide the band-pass filtering of the analog signals prior to encoding and after decoding. these combination devices perform the encoding and decoding of voice and call progress tones as well as the signaling and supervision information. these devices contain patented circuitry to achieve low transmit channel idle noise and are not recommended for applications in which the composite signals on the transmit side are below 55 dbm0. the tcm29c13a, tcm29c14a, tcm29c16a, and tcm29c17a are characterized for operation from 0 c to 70 c. the tcm129c13a, tcm129c14a, tcm129c16a, and tcm129c17a are characterized for operation from 40 c to 85 c. functional block diagram successive approximation buffer pwro+ pwro gsr gsx anlg in anlg in+ transmit section receive section sigr 2 control section pdn control logic dclkr pcm in input register digital- to-analog control logic reference sample and hold and dac analog- to-digital control logic gain set filter reference fsx/tsxe autozero output register tsx /dclkx pcm out comparator sample and hold and dac filter s sigx/asel clkx clksel anlg loop 2 fsr/tsre clkr 2 anlg gnd dgtl gnd v bb v cc 3 2 tcm29c14a and tcm129c14a only. 3 tcm29c13a, tcm29c16a, tcm29c17a, tcm129c13a, tcm129c16a, and tcm129c17a only
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 3 post office box 655303 ? dallas, texas 75265 terminal functions terminal no. name tcm29c13a tcm129c13a tcm29c14a tcm129c14a tcm29c16a tcm29c17a tcm129c16a tcm129c17a i/o description anlg gnd 16 20 13 analog ground return for all internal voice circuits. anlg gnd is internally connected to dgtl gnd. anlg in + 17 21 i noninverting analog input to uncommitted transmit operational amplifier. anlg in + is internally connected to anlg gnd on tcm29c16a, tcm129c16a, tcm29c17a, and tcm129c17a. anlg in 18 22 14 i inverting analog input to uncommitted transmit operational amplifier. anlg loop 7 i provides loopback test capability. when anlg loop is high, pwro + is internally connected to anlg in. clkr 11 13 9 i receive master clock and data clock for the fixed-data-rate mode. receive master clock only for variable-data-rate mode. clkr and clkx are internally connected together for the tcm29c13a, tcm29c16a, tcm29c17a, tcm129c13a, tcm129c16a, and tcm129c17a. clksel 6 6 i clock-frequency selection. clksel must be connected to v bb , v cc , or gnd to reflect the master clock frequency. when tied to v bb , clk is 2.048 mhz. when tied to gnd, clk is 1.544 mhz. when tied to v cc , clk is 1.536 mhz. clkx 11 14 9 i transmit master clock and data clock for the fixed-data-rate mode. transmit master clock only for variable-date-rate mode. clkr and clkx are internally connected for the tcm29c13a, tcm29c16a, tcm29c17a, tcm129c13a, tcm129c16a, and tcm129c17a. dclkr 7 9 5 i selects fixed- or variable-data-rate operation. when dclkr is connected to v bb , the device operates in the fixed-data-rate mode. when dclkr is not connected to v bb , the device operates in the variable-data-rate mode and dclkr becomes the receiver data clock, which operates at frequencies from 64 khz to 2.048 mhz. dgtl gnd 10 12 8 digital ground for all internal logic circuits. dgtl gnd is internally connected to anlg gnd. fsr/tsre 9 11 7 i frame-synchronization clock input/time-slot enable for receive channel. in the fixed-data-rate mode, fsr distinguishes between signaling and nonsignaling frames by a double- or single-length pulse, respectively. in the variable-data-rate mode, this signal must remain high for the duration of the time slot. the receive channel enters the standby state when fsr is ttl low for 300 ms. fsx/tsxe 12 15 10 i frame-synchronization clock input/time-slot enable for transmit channel. fsx/tsxe operates independently of, but in an analagous manner to, fsr/tsre. the transmit channel enters the standby state when fsx is low for 300 ms. gsr 4 4 i input to the gain-setting network on the output power amplifier. transmission level can be adjusted over a 12-db range depending upon the voltage at gsr. gsx 19 23 15 o output terminal of internal uncommitted operational amplifier. internally, this is the voice signal input to the transmit filter.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 4 post office box 655303 ? dallas, texas 75265 terminal functions (continued) terminal no. name tcm29c13a tcm129c13a tcm29c14a tcm129c14a tcm29c16a tcm29c17a tcm129c16a tcm129c17a i/o description pcm in 8 10 6 i receive pcm input. pcm data is clocked in on pcm in on eight consecutive negative transitions of the receive data clock, which is clkr in fixed-data-rate timing and dclkr in variable-data-rate timing. pcm out 13 16 11 o transmit pcm output. pcm data is clocked out on pcm out on eight consecutive positive transitions of the transmit data clock, which is clkx in fixed-data-rate timing and dclkx in variable-data-rate timing. pdn 5 5 4 i power-down select. the device is inactive with a ttl low-level input to this pdn and active with a ttl high-level input to this pdn . pwro + 2 2 2 o noninverting output of power amplifier. pwro + drives transformer hybrids or high-impedance loads directly in either a differential or a single-ended configuration. pwro 3 3 3 o inverting output of power amplifier. pwro is functionally identical with and complementary to pwro +. sigr 8 o signaling bit output, receive channel. in the fixed-data-rate mode, sigr outputs the logical state of the 8th bit (lsb) of the pcm word in the most recent signaling frame. sigx/asel 15 18 i a-law and m -law operation select. when connected to v bb , a-law is selected. when connected to v cc or gnd, m -law is selected. when not connected to v bb , it is a ttl-level input that is transmitted as the eighth bit (lbs) of the pcm word during signaling frames on pcm out (tcm29c14a and tcm129c14a only). sigx/asel is internally connected to provide m -law operational for tcm29c16a and tcm129c16a and a-law operation for tcm29c17a and tcm129c17a. tsx /dclkx 14 17 12 i/o transmit channel time-slot strobe (output) or data clock (input) for the transmit channel. in the fixed-data-rate mode, tsx /dclkx is an open-drain output to be used as an enable signal for a 3-state output buffer. in the variable-data-rate mode, dclkx becomes the transmit data clock, which operates at a ttl level from 64 khz to 2.048 mhz. v bb 1 1 1 most negative supply voltage. input is 5 v 5%. v cc 20 24 16 most positive supply voltage. input is 5 v 5%.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 5 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc (see note 1) 0.3 v to 15 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o 0.3 v to 15 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i 0.3 v to 15 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital ground voltage range 0.3 v to 15 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total dissipation at (or below) 25 c free-air temperature 1375 mw . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a : tcm29cxxa 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcm129cxxa 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: dw or n package 260 c . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: voltage values for maximum ratings are with respect to v bb . recommended operating conditions (see note 2) min nom max unit v cc supply voltage (see note 3) 4.75 5 5.25 v v bb supply voltage 4.75 5 5.25 v digital ground voltage, with respect to anlg gnd 0 v v ih high-level input voltage, all inputs except clksel 2.2 v v il low-level input voltage, all inputs except clksel 0.8 v 2.048 mhz v bb v bb +0.5 v i clksel input voltage 1.544 mhz 0 0.5 v 1.536 mhz v cc 0.5 v cc r l load resistance gsx 10 k w r l load resistance pwro + and/or pwro 300 w c l load ca p acitance gsx 50 p f c l load capacitance pwro + and/or pwro 100 pf t a o p erating free air tem p erature tcm29cxxa 0 70 c t a operating free - air temperat u re tcm129cxxa 40 85 c notes: 2. to avoid possible damage to these cmos devices and resulting reliability problems, the power-up procedure described in the device power-up sequence paragraphs later in this document should be followed. 3. voltage is at analog inputs and outputs. v cc and v bb terminals are with respect to anlg gnd. all other voltages are referenced to dgtl gnd unless otherwise noted.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 6 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current, f dclk = 2.048 mhz, outputs not loaded parameter test conditions tcm29cxxa tcm129cxxa unit parameter test conditions min typ 2 max min typ 2 max unit sl t operating 7 9 8 13 i cc supply current from v cc standby fsx or fsr at v il after 300 ms 0.5 1.1 0.7 1.5 ma cc from v cc power down pdn v il after 300 ms 0.3 0.9 0.4 1 sl t operating 7 9 8 13 i bb supply current from v bb standby fsx or fsr at v il after 300 ms 0.5 1 0.7 1.5 ma bb from v bb power down pdn v il after 300 ms 0.3 0.9 0.4 1.1 operating 70 90 80 130 p d power dissipation standby fsx or fsr at v il after 300 ms 5 10 7 15 mw power down pdn v il after 300 ms 3 8 4 10 2 all typical values are at v bb = 5 v, v cc = 5 v, and t a = 25 c. ground terminals parameter test conditions min typ max unit dc resistance between anlg gnd and dgtl gnd 34 w digital interface parameter test condi- tcm29cxxa tcm129cxxa unit parameter tions min typ 2 max min typ 2 max unit v oh high level out p ut voltage pcm out i oh = 9.6 ma 2.4 2.4 v v oh high - le v el o u tp u t v oltage sigr i oh = 1.2 ma 2.4 2.4 v v ol low-level output voltage at pcm out, tsx, sigr i ol = 3.2 ma 0.4 0.5 v i ih high-level input current, any digital input v i = 2.2 v to v cc 10 12 m a i il low-level input current, any digital input v i = 0 to 0.8 v 10 12 m a c i input capacitance 5 10 5 10 pf c o output capacitance 5 5 pf 2 all typical values are at v bb = 5 v, v cc = 5 v, and t a = 25 c. transmit amplifier input parameter test conditions min typ 2 max unit input current at anlg in +, anlg in 100 na input offset voltage at anlg in +, anlg in v i = 2.17 v to 2.17 v 25 mv common-mode rejection at anlg in +, anlg in 55 db open-loop voltage amplification at gsx 5000 open-loop unity-gain bandwidth at gsx 1 mhz input resistance at anlg in +, anlg in 10 m w 2 all typical values are at v bb = 5 v, v cc = 5 v, and t a = 25 c. receive filter output parameter test conditions min typ 2 max unit output offset voltage at pwro+, pwro (single ended) relative to anlg gnd 80 180 mv output resistance at pwro+, pwro 1 w 2 all typical values are at v bb = 5 v, v cc = 5 v, and t a = 25 c.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 7 post office box 655303 ? dallas, texas 75265 gain and dynamic range, v cc = 5 v, v bb = 5 v, t a = 25 c (see notes 4, 5, and 6) (unless otherwise noted) parameter test conditions min typ max unit encoder milliwatt res p onse (transmit gain tolerance) signal input = 1.064 vrms for m -law, dbm0 encoder milli w att response (transmit gain tolerance) g m , signal input = 1.068 vrms for a-law dbm0 encoder milliwatt response (nominal supplies and temperature) t a = 0 c to 70 c, supplies = 5 % 0.08 db digital milliwatt response (receive tolerance gain) relative to zero-transmission level point signal input per ccitt g.711, output signal = 1 khz dbm0 digital milliwatt response variation with temperature and supplies t a = 0 c to 70 c, supplies = 5% 0.08 db m -law r l = 600 w 2.76 zero transmission level p oint transmit channel (0 dbm0) a-law r l = 600 w 2.79 dbm zero - transmission - le v el point , transmit channel (0 dbm0) m -law r l = 900 w 1 dbm a-law r l = 900 w 1.03 m -law r l = 600 w 5.76 zero transmission level p oint receive channel (0 dbm0) a-law r l = 600 w 5.79 dbm zero - transmission - le v el point , recei v e channel (0 dbm0) m -law r l = 900 w 4 dbm a-law r l = 900 w 4.03 notes: 4. unless otherwise noted, the analog input is a 0-dbm0, 1020-hz sine wave, where 0 dbm0 is defined as the zero-reference point of the channel under test. this corresponds to an analog signal input of 1.064 vrms or an output of 1.503 vrms. 5. the input amplifier is set for noninverting unity gain. the digital input is a pcm bit stream generated by passing a 0-dbm0, 1020-hz sine wave through an ideal encoder. 6. receive output is measured single ended in the maximum-gain configuration. to set the output amplifier for maximum gain, gsr is connected to pwro and the output is taken at pwro +. all output levels are (sin x)/x corrected. gain tracking over recommended ranges of supply voltage and operating free-air temperature, reference level = 10 dbm0 parameter test conditions min max unit 3 input level 40 dbm0 0.25 transmit gain-tracking error, sinusoidal input 40 > input level 50 dbm0 0.5 db 50 > input level 55 dbm0 1.2 3 input level 40 dbm0 0.25 receive gain-tracking error, sinusoidal input 40 > input level 50 dbm0 0.5 db 50 > input level 55 dbm0 1.2
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 8 post office box 655303 ? dallas, texas 75265 noise over recommended ranges of supply voltage and operating free-air temperature range parameter test conditions min typ 2 max unit transmit noise, c-message weighted 3 anlg in+ = anlg gnd, anlg in = gsx 1 7 dbrnc0 transmit noise, c-message weighted with 8-bit signaling (tcm129c14a and tcm29c14a only) anlg in+ = anlg gnd, 6th frame signaling anlg in = gsx, 13 dbrnc0 transmit noise, psophometrically weighted3 anlg in+ = anlg gnd, anlg in = gsx 82 80 dbm0p receive noise, c-message-weighted quiet code pcm in = 1 1111111 ( m -law), pcm in = 10101010 (a-law), measured at pwro + 2 5 dbrnc0 receive noise, c-message-weighted sign bit toggled input to pcm in is zero code with sign bit toggled at 1-khz rate 3 6 dbrnc0 receive noise, psophometrically weighted pcm = lowest positive decode level 81 dbm0p 2 all typical values are at v bb = 5 v, v cc = 5 v, and t a = 25 c. 3 this parameter is achieved through the use of patented circuitry and is not recommended for applications in which composite sig nals on the transmit side are below 55 dbm0. power supply rejection ratio and crosstalk attenuation over recommended ranges of supply voltage and operating free-air temperature parameter test conditions min typ 2 max unit v cc supply-voltage rejection ratio, 0 f < 30 khz idle channel, su pp ly signal = 200 mv( p eak to p eak) 40 db cc ygj , transmit channel 30 f < 50 khz supply signal = 200 mv(peak - to - peak) , f measured at pcm out 45 db v bb supply-voltage rejection ratio, 0 f < 30 khz idle channel, su pp ly signal = 200 mv( p eak to p eak) 35 db bb ygj , transmit channel 30 f < 50 khz supply signal = 200 mv(peak - to - peak) , f measured at pcm out 55 db v cc supply-voltage rejection ratio, 0 f < 30 khz idle channel, su pp ly signal = 200 mv( p eak to p eak) 40 db cc ygj , receive channel (single ended) 30 f < 50 khz supply signal = 200 mv(peak - to - peak) , f measured at pwro + 45 db v bb supply-voltage rejection ratio, 0 f < 30 khz idle channel, su pp ly signal = 200 mv( p eak to p eak) 40 db bb ygj , receive channel (single ended) 30 f < 50 khz supply signal = 200 mv(peak - to - peak) , narrow-band f measured at pwro + 45 db crosstalk attenuation, transmit to receive (single ended) anlg in+ = 0 dbm0, f = 1.02 khz, unity gain, pcm in = lowest decode level, measured at pwro + 75 db crosstalk attenuation, receive to transmit (single ended) pcm in = 0 dbm0, f = 1.02 khz, measured at pcm out 75 db 2 all typical values are at v bb = 5 v, v cc = 5 v, and t a = 25 c.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 9 post office box 655303 ? dallas, texas 75265 distortion over recommended ranges of supply voltage and operating free-air temperature parameter test conditions min typ 2 max unit t it i l t di t ti ti i id l 0 anlg in+ 30 dbm0 36 transmit signal-to-distortion ratio, sinusoidal in p ut (ccitt g 712 method 2) 30 > anlg in+ 40 dbm0 30 db in ut (ccitt g . 712 method 2) 40 > anlg in+ 45 dbm0 25 r i i l t di t ti ti i id l 0 anlg in+ 30 dbm0 36 receive signal-to-distortion ratio, sinusoidal in p ut (ccitt g 712 method 2) 30 > anlg in+ 40 dbm0 30 db in ut (ccitt g . 712 method 2) 40 > anlg in+ 45 dbm0 25 transmit single-frequency distortion products at&t advisory #64 (3.8), input signal = 0 dbm0 46 dbm0 receive single-frequency distortion products at&t advisory #64 (3.8), input signal = 0 dbm0 46 dbm0 ccitt g.712 (7.1) 35 intermodulation distortion, end to end spurious ccitt g.712 (7.2) 49 dbm0 , out-of-band signals, end to end ccitt g.712 (6.1) 25 dbm0 ccitt g.712 (9) 40 transmit absolute delay time to pcm out fixed-data rate, f clkx = 2.048 mhz, 245 m s transmit absolute delay time to pcm out input to anlg in + 1.02 khz at 0 dbm0 f = 500 hz to 600 hz 170 transmit differential envelope delay time f = 600 hz to 1000 hz 95 m s y relative to transmit absolute delay time f = 1000 hz to 2600 hz 45 m s f = 2600 hz to 2800 hz 105 receive absolute delay time to pwro + fixed data rate, digital input is dmw codes f clkr = 2.048 mhz, 190 m s f = 500 hz to 600 hz 45 receive differential envelope delay time f = 600 hz to 1000 hz 35 m s y relative to transmit absolute delay time f = 1000 hz to 2600 hz 85 m s f = 2600 hz to 2800 hz 110 2 all typical values are at v bb = 5 v, v cc = 5 v, and t a = 25 c. transmit filter transfer over recommended ranges of supply voltage and operating free-air temperature (see figure 1) parameter test conditions min max unit 16.67 hz 30 50 hz 25 60 hz 23 gain relative to gain at 1 02 khz input amplifier set for unity gain, noninverting maximum gain out p ut 200 hz 1.8 0.125 db gain relati v e to gain at 1 . 02 kh z noninverting maximum gain output , input si g nal at anlg in + is 0 dbm0 300 hz to 3 khz 0.15 0.15 db in ut signal at anlg in + is 0 dbm0 3.3 khz 0.35 0.15 3.4 khz 1 0.1 4 khz 14
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 10 post office box 655303 ? dallas, texas 75265 receive filter transfer over recommended ranges of supply voltage and operating free-air temperature (see figure 2) parameter test conditions min max unit below 200 hz 0.15 200 hz 0.5 0.15 300 hz to 3 khz 0.15 0.15 gain relative to gain at 1.02 khz input signal at pcm in is 0 dbm0 3.3 khz 0.35 0.15 db 3.4 khz 1 0.1 4 khz 14 4.6 khz 30 timing requirements clock timing requirements over recommended ranges of supply voltage and operating free-air temperature (see figure 3 and 4) min nom max unit t c(clk) clock period for clkx, clkr (2.048-mhz systems) 488 ns t r , t f rise and fall times for clkx and clkr 5 30 ns t w(clk) pulse duration for clkx and clkr (see note 7) 220 ns t w(dclk) pulse duration, dclk (f dclk = 64 hz to 2.048 mhz) (see note 7) 220 ns clock duty cycle, [t w(clk) /t c(clk) ] for clkx and clkr 45% 50% 55% note 7: fsx clk must be phase locked with clkx. fsr clk must be phase locked with clkr. transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see figure 3) min max unit t d(fsx) frame-sync delay time 100 t c(clk) 100 ns t su(sigx) setup time before bit 7 falling edge of clkx (tmc29c14a and tcm129c14a only) 0 ns t h(sigx) hold time after bit 8 falling edge of clkx (tcm29c14a and tcm129c14a only) 0 ns receive timing requirements over recommended ranges of supply voltages and operating free-air temperature, fixed-data-rate mode (see figure 4) min max unit t d(fsr) frame-sync delay time 100 t c(clk) 100 ns t su(pcm in) receive data setup time 50 ns t h(pcm in) receive data hold time 60 ns transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode (see figure 5) min max unit t d(tsdx) time-slot delay time from dclkx (see note 8) 140 t d(dclkx) 140 ns t d(fsx) frame sync delay time 100 t c(clk) 100 ns t c(dclkx) clock period for dclkx 488 15620 ns note 8: t fslx minimum requirement overrides the t d(tsdx) maximum requirement for 64-khz operation.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 11 post office box 655303 ? dallas, texas 75265 receive timing requirements over recommended ranges of supply voltages and operating free-air temperature, variable-data-rate mode (see figure 6) min max unit t d(tsdr) time-slot delay time from dclkr (see note 9) 140 t d(dclkr) 140 ns t d(fsr) frame-sync delay time 100 t c(clk) 100 ns t su(pcm in) receive data setup time 50 ns t h(pcm in) receive data hold time 60 ns t c(dclkr) data clock period 488 15620 ns t (ser) time-slot end receive time 0 ns note 9: t fslr minimum requirement overrides the t d(tsdr) maximum requirement for 64-khz operation. 64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode min max unit t fslx transmit frame-sync minimum down time fsx = ttl high for remainder of frame 488 ns t fslr receive frame-sync minimum down time fsx = ttl high for remainder of frame 1952 ns t w(dclk) pulse duration, data clock 10 m s switching characteristics delay time over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see figure 3 and 4) parameter test conditions min max unit t pd1 from rising edge of transmit clock to bit 1 data valid at pcm out (data enable time on time-slot entry) (see note 10) c l = 0 to 100 pf 0 145 ns t pd2 from rising edge of transmit clock bit n to bit n data valid at pcm out (data valid time) c l = 0 to 100 pf 0 145 ns t pd3 from falling edge of transmit clock bit 8 to bit 8 hi-z at pcm out (data float time on time-slot exit) (see note 10) c l = 0 60 215 ns t pd4 from rising edge of transmit clock bit 1 to tsx active (low) (time-slot enable time) c l = 0 to 100 pf 0 145 ns t pd5 from falling edge of transmit clock bit 8 to tsx inactive (high) (time-slot disable time) (see note 10) c l = 0 60 190 ns t pd6 from rising edge of channel time slot to sigr update (tcm29c14a and tcm129c14a only) 0 2 m s note 10: timing parameters t pd1 , t pd3 , and t pd5 are referenced to the high-impedance state. delay time over recommended ranges of operating conditions, variable-data-rate mode (see note 11 and figure 5) parameter test conditions min max unit t pd7 delay time from dclkx 0 100 ns t pd8 delay from time-slot enable to pcm out c l = 0 to 100 pf 0 50 ns t pd9 delay from time-slot disable to pcm out 0 80 ns t pd10 delay time from fsx t d(tsdx) = 80 ns 0 140 ns note 11: timing parameters t pd8 and t pd9 are referenced to the high-impedance state.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 12 post office box 655303 ? dallas, texas 75265 parameter measurement information clkr and clkx selection requirements for dsp-based applications clkx and clkr must be selected as follows: clksel clkr, clkx (between 1 mhz to 3 mhz) device type 5v 2 = (256) (frame sync frequency) tcm29c13a/14a/16a/17a 5 v 2 = (256) (frame - s y nc freq u enc y ) tcm129c13a/14a/16a/17a 0v = (193) (frame sync frequency) tcm29c13a/14a 0 v = (193) (frame - s y nc freq u enc y ) tcm129c13a/14a 5v = (192) (frame sync frequency) tcm29c13a/14a 5 v = (192) (frame - s y nc freq u enc y ) tcm129c13a/14a 2 clksel is internally set to 5 v for tcm29c16a/1a7 and tcm129c16a/17a e.g., for frame-sync frequency = 9.6 khz clksel clkr, clkx (between 1 mhz to 3 mhz) device type 5v 2 = 2 4576 mhz tcm29c13a/14a/16a/17a 5 v 2 = 2 . 4576 mh z tcm129c13a/14a/16a/17a 0v = 1 8528 mhz tcm29c13a/14a 0 v = 1 . 8528 mh z tcm129c13a/14a 5v = 1 8432 mhz tcm29c13a/14a 5 v = 1 . 8432 mh z tcm129c13a/14a 2 clksel is internally set to 5 v for tcm29c16a/1a7 and tcm129c16a/17a. corner frequency at 8-khz frame-sync frequency = 3 khz, therefore, the corner frequency = (3/8) (frame-sync frequency for nonstandard frame sync).
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 13 post office box 655303 ? dallas, texas 75265 parameter measurement information 0 1 0 10 20 30 40 50 50 40 30 20 10 0 1 0 10 k 1 k 100 50 10 gain relative to gain at 1 khz db f frequency hz 0.15 db 3000 hz expanded scale 60 60 0.10 db 3400 hz typical filter transfer function 32 db 4600 hz 14 db 4000 hz 0.15 db 3300 hz 0.15 db 3000 hz typical filter transfer function 0.15 db 300 hz 0.125 db 200 hz 0.15 db 300 hz 1.8 db 200 hz 23 db 60 hz 25 db 50 hz 30 db 16.67 hz 0.35 db 3300 hz 1db 3400 hz figure 1. transmit filter transfer characteristics
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 14 post office box 655303 ? dallas, texas 75265 parameter measurement information 30 db 4800 hz 14 db 4000 hz 0 1 0 10 20 30 40 50 50 40 30 20 10 0 1 0 10 k 1 k 100 gain relative to gain at 1 khz db f frequency hz expanded scale 1 2 1 2 0.15 db 200 hz 0.15 db 300 hz 0.15 db 3000 hz 0.15 db 3300 hz 0.10 db 3400 hz 1db 3400 hz 0.15 db 3000 hz 0.35 db 3300 hz 0.15 db 300 hz 0.5 db 200 hz note a: this is a typical transfer function of the receive filter component. figure 2. receive filter transfer characteristics
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 15 post office box 655303 ? dallas, texas 75265 parameter measurement information t d(fsx) clkx fsx (nonsignaling frames) clkx pcm out tsx t r t f t w(clk) t c(clk) time slot 1 t d(fsx) 12345678 12345678 time slot n frame synchronization timing t pd1 t pd2 t pd3 t pd5 t pd4 bit 1 2 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 2 output timing t d(fsx) fsx (signaling frames) valid t su(sigx) t h(sigx) don't care don't care sigx t d(fsx) 2 bit 1 = msb = sign bit and is clocked in first on pcm in or clocked out first on pcm out. bit 8 = lsb = least significant bit a nd is clocked in last on pcm in or is clocked out last on pcm out. note a: inputs are driven from 0.45 v to 2.4 v. time intervals are referenced to 2 v if the high level is indicated and 0.8 v if the low level is indicated. figure 3. transmit timing (fixed-data rate)
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 16 post office box 655303 ? dallas, texas 75265 parameter measurement information clkr fsr frames) clkr pcm in time slot 1 12345678 t d(fsr) t d(fsr) t r t f t w(clk) t c(clk) frame synchronization timing 12345678 time slot n t su(pcm in) t h(pcm in) t pd6 bit 1 2 valid bit 2 valid bit 3 valid bit 4 valid bit 5 valid bit 6 valid bit 7 valid bit 8 2 valid input timing t d(fsr) valid valid sigr fsr (signaling frames) t d(fsr) (nonsignaling 2 bit 1 = msb = sign bit and is clocked in first on pcm in or clocked out first on pcm out. bit 8 = lsb = least significant bit a nd is clocked in last on pcm in or is clocked out last on pcm out. note a: inputs are driven from 0.45 v to 2.4 v. time intervals are referenced to 2 v if the high level is indicated and 0.8 v if the low level is indicated. figure 4. receive timing (fixed-data rate)
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 17 post office box 655303 ? dallas, texas 75265 parameter measurement information time slot t d(tsdx) t pd10 fsx dclkx clkx pcm out 12345678 bit 1 2 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 2 t d(fsx) t pd7 t pd9 t pd8 figure 5. transmit timing (variable-data rate) fsr dclkr clkr pcm in 12345678 t d(tsdr) t d(fsr) t su(pcm in) t h(pcm in) t (ser) bit 1 2 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 2 don't care figure 6. receive timing (variable-data rate) 2 bit 1 = msb = sign bit and is clocked in first on pcm in or clocked out first on pcm out. bit 8 = lsb = least significant bit a nd is clocked in last on pcm in or is clocked out last on pcm out. note a: all timing parameters are referenced to v ih and v il except t pd8 and t pd9 , which references the high-impedance state.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 18 post office box 655303 ? dallas, texas 75265 principles of operation system reliability and design considerations tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tcm129c14a, tcm129c16a, and tcm129c17a system reliability and design considerations are described in the following paragraphs. latch-up latch-up is possible in all cmos devices. it is caused by the firing of a parasitic scr that is present due to the inherent nature of cmos. when a latch-up occurs, the device draws excessive amounts of current and will continue to draw heavy current until power is removed. latch-up can result in permanent damage to the device if supply current to the device is not limited. even though the tcm29cxxa and tcm129cxxa devices are heavily protected against latch-up, it is still possible to cause latch-up under certain conditions in which excess current is forced into or out of one or more terminals. latch-up can occur when the positive supply voltage drops momentarily below ground, when the negative supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after power has been applied but before the ground is connected. this can happen if the device is hot-inserted into a card with the power applied, or if the device is mounted on a card that has an edge connector, and the card is hot-inserted into a system with the power on. to help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased schottky diode (with a forward voltage drop of less than or equal to 0.4 v e 1n5711 or equivalent), between each power supply and gnd (see figure 7). if it is possible that a tcm29cxxa- or tcm129cxxa-equipped card that has an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground edge connector traces are longer than the power and signal traces so that the card ground is always the first to make contact. device power-up sequence latch-up also can occur if a signal source is connected without the device being properly grounded. a signal applied to one terminal could then find a ground through another signal terminal on the device. to ensure proper operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following power-up sequence always be used: 1. ensure no signals are applied to the device before the power-up sequence is complete. 2. connect gnd. 3. apply v bb (most negative voltage). 4. apply v cc (most positive voltage). 5. force a power down condition in the device. 6. connect clocks. 7. release the power-down condition. 8. apply fsx and/or fxr synchronization pulses. 9. apply signal inputs. when powering down the device, this procedure should be followed in the reverse order.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 19 post office box 655303 ? dallas, texas 75265 principles of operation v cc dgnd v bb figure 7. diode configuration for latch-up protection circuitry internal sequencing on the transmit channel, digital outputs pcm out and tsx are held in the high-impedance state for approximately four frames (500 m s) after power up or application of v bb or v cc . after this delay, pcm out, tsx , and signaling are functional and occur in the proper time slot. the analog circuits on the transmit side require approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. valid digital information, such as on/off hook detection, is available almost immediately, while analog information is available after some delay. on the receive channel, the digital output sigr is also held low for a maximum of four frames after power up or application of v bb or v cc . sigr remains low until it is updated by a signalling frame. to further enhance system reliability, pcm out and tsx are placed in the high-impedance state approximately 20 m s after an interruption of clkx. sigr is held low approximately 20 m s after an interruption of clkr. these interruptions could possibly occur with some kind of fault condition. power-down and standby operations to minimize power consumption, a power-down mode and three standby modes are provided. for power down, an external low signal is applied to pdn . in the absence of a signal, pdn is internally pulled up to a high logic level and the device remains active. in the power-down mode, the average power consumption is reduced 15 mw. three standby modes give the user the options of placing the entire device on standby, placing only the transmit channel on standby, or placing only the receive channel on standby. to place the entire device on standby, both fsx and fsr are held low. for transmit-only operation (receive channel on standby), fsx is high and fsr is held low. for receive-only operation (transmit section on standby), fsr is high and fsx is held low. when the entire device is in standby mode, power consumption is reduced to an average of 3 mw. see table 1 for power-down and standby procedures. table 1. power-down and standby procedures device status procedure typical power consumption digital output status power down pdn low 3 mw tsx and pcm out are in the high-impedance state; sigr goes low within 10 m s. entire device on standby fsx and fsr are low 3 mw tsx and pcm out are in the high-impedance state; sigr goes low within 300 ms. only transmit on standby fsx is low, fsr is high 40 mw tsx and pcm out are placed in the high-impedance state within 300 ms. only receive on standby fsr is low, fsx is high 30 mw sigr is placed in the high-impedance state within 300 ms.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 20 post office box 655303 ? dallas, texas 75265 principles of operation fixed-data-rate timing (see figure 8) fixed-data-rate timing is selected by connecting dclkr to v bb and uses master clocks clkx and clkr, frame-synchronizer clocks fsx and fsr, and the output tsx . fsx and fsr are 8-khz inputs that set the sampling frequency and distinguish between signaling and nonsignaling frames by their pulse durations. a frame synchronization pulse one master-clock period long designates a nonsignaling frame, while a double-length sync pulse enables the signaling function (tcm12914a and tcm29c14a only). data is transmitted on pcm out on the first eight positive transitions of clkx following the rising edge of fsx. data is received on pcm in on the first eight falling edges of clkr following fsr. a digital-to-analog (d/a) conversion is performed on received digital word, and the resulting analog sample is held on an internal sample-and-hold capacitor until transferred to the receive filter. the clock-selection terminal (clksel) is used to select the frequency of clkx and clkr (tcm29c13a, tcm29c14a, tcm129c13a, and tcm129c14a only). the tcm29c13a, tcm29c14a, tcm129c13a, and tcm129c14a fixed-data-rate mode can operate with frequencies of 1.536 mhz, 1.544 mhz, or 2.048 mhz. the tcm29c16a, tcm29c17a, tcm129c16a, and tcm129c17a fixed-data-rate mode operates at 2.048 mhz only. 12345678 12345678 192 /193 / 256 ts1x other time slots ts1x transmit signal frame don't care don't care valid b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 sigx 12345678 12345678 192 /193 /256 ts1r other time slots ts1r receive signal frame previous value b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 sigr 9 192 /193 /256 new value clkx fsx pcm out tsx sigx clkr fsr pcm in sigr 192/193/256 figure 8. signaling timing (fixed-data rate only)
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 21 post office box 655303 ? dallas, texas 75265 principles of operation variable-data-rate timing variable-data-rate timing is selected by connecting dclkr to the bit clock for the receive pcm highway rather than to v bb . it uses master clocks clkx and clkr, bit clocks dclkx and dclkr, and frame-synchronization clocks fsx and fsr. variable-data-rate timing allows for a flexible data frequency. the frequency of the bit clocks can be varied from 64 khz to 2.048 mhz. master clocks in the tcm129c13a, tcm129c14a, tcm29c13a, and tcm29c14a are restricted to frequencies of operation of 1.536 mhz, 1.544 mhz, or 2.048 mhz as in the fixed-data-rate timing mode. the master clock for the tcm129c16a, tcm129c17a, tcm29c16a, and tcm29c17a is restricted to 2.048 mhz. when the fsx/tsxe is high, pcm data is transmitted from pcm out onto the highway on the next eight consecutive positive transitions of dclkx. similarly, while the fsr/tsre input is high, the pcm word is received from the highway by pcm in on the next eight consecutive negative transitions of dclkr. the transmitted pcm word is repeated in all remaining time slots in the 125- m s frame as long as dclkx is pulsed and fsx is held high. this feature, which allows the pcm word to be transmitted to the pcm highway more than once per frame if desired, is available only with variable-data-rate timing. signaling is allowed only in the fixed-data-rate mode because the variable-data-rate mode provides no means with which to specify a signaling frame. signaling only the tcm29c14a provides 8th-bit signaling in the fixed-data-rate timing mode. transmit and receive signaling frames are independent of each other and are selected by a double-width frame-sync pulse on the appropriate channel. during a transmit signaling frame, the signal present on sigx is substituted for the least significant bit (lsb) of the encoded pcm word. in a receive signaling frame, the codec decodes the seven most significant bits in accordance with ccitt g.733 recommendations and outputs the logical state of the lsb on sigr until it is updated in the next signaling frame. timing relationships for signaling operations are shown in figure 8. the signaling path is used to transmit digital signaling information such as ring control, rotary dial pulses, and off-hook and disconnect supervision. the voice path is used to transmit prerecorded messages as well as the call progress tones: dial tone, ring-back tone, busy tone, and reorder tone.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 22 post office box 655303 ? dallas, texas 75265 principles of operation analog loopback a distinctive feature of the tcm29c14a and tcm129c14a is the analog loopback capability. with this feature, the user can test the line circuit remotely by comparing the signals sent into the receive channel (pcm in) with those generated on the transmit channel (pcm out). the test is accomplished by sending a control signal that internally connects the analog input and output ports. when anlg loop is ttl high, the receive output (pwro+) is internally connected to anlg in +, gsr is internally connected to pwro , and anlg in is internally connected to gsx (see figure 8). _ + _ + a/d d/a anlg in + anlg in gsx anlg loop gsr pcm out digitized pcm loopback response pcm in digitized pcm test tone transmit voice pwro + pwro figure 9. tcm29c14a and tcm129c14a analog loopback configuration due to the difference in the transmit and receive transmission levels, a 0-dbm0 code into pcm in emerges from pcm out as a 3-dbm0 code, an implicit gain of 3 db. because of this, the maximum signal that can be tested by analog loopback is 0 dbm0. precision voltage references voltage references that determine the gain dynamic range characteristics of the device are generated internally. no external components are required to provide the voltage references. a difference in subsurface charge density between two suitably implanted mos devices is used to derive a temperature- and bias-stable reference voltage, which is calibrated during the manufacturing process. separate references are supplied to the transmit and receive sections, and each is calibrated independently. each reference value is then further trimmed in the gain-setting operational amplifiers to a final precision value. manufacturing tolerances of typically 0.04 db can be achieved in absolute gain for each half channel, providing the user a significant margin to compensate for error in other system components. conversion laws the tcm29c13a, tcm29c14a, tcm129c13a, and tcm129c14a provide pin-selectable m -law operation as specified by ccitt g.711 recommendation. a-law operation is selected when asel is connected to v bb , and m -law operation is selected by connecting asel to v cc or gnd. signaling is not allowed during a-law operation. if m -law operation is selected, sigx is a ttl-level input that can be used in the fixed-data-rate timing mode to modify the lsb of the pcm output is signaling frames. the tcm29c16a and tcm129c16a are m -law only; the tcm29c17a and tcm129c17a are a-law only.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 23 post office box 655303 ? dallas, texas 75265 principles of operation transmit operation transmit filter the input section provides gain adjustment in the pass band by means of an on-chip uncommitted operational amplifier. the load impedance to ground (anlg gnd) at the amplifier output (gsx) must be greater than 10 k w in parallel with less than 50 pf. the input signal on anlg in + can be either ac or dc coupled. the input operational amplifier can also be used in the inverting mode or differential amplifier mode. a low-pass antialiasing filter section is included on the device. this section provides 35-db attenuation at the sampling frequency. no external components are required to provide the necessary antialiasing function for the switched-capacitor section of the transmit filter. the pass-band section provides flatness and stop-band attenuation that fulfills the at&t d3/d4 channel bank transmission specification and ccitt recommendation g.712. the device specifications meet or exceed digital class 5 central office switching-systems requirements. a high-pass section configuration has been chosen to reject low-frequency noise from 50-hz and 60-hz power lines, 17-hz european electric railroads, ringing frequencies and their harmonics, and other low-frequency noise. even with the high rejection at these frequencies, the sharpness of the band edge gives low attenuation at 200 hz. this feature allows the use of low-cost transformer hybrids without external components. encoding the encoder internally samples the output of the transmit filter and holds each sample on an internal sample-and-hold capacitor. the encoder performs an analog-to-digital conversion on a switched-capacitor array. digital data representing the sample is transmitted on the first eight data clock bits of the next frame. the autozero circuit corrects for dc offset on the input signal to the encoder. the autozero circuit uses the sign-bit-averaging technique. the sign bit from the encoder output is long-term averaged and subtracted from the input to the encoder. all dc offset is removed from the encoder input waveform. receive operation decoding the serial pcm word is received at pcm in on the first eight data clock bits of the frame. digital-to-analog conversion is performed, and the corresponding analog sample is held on an internal sample-and-hold capacitor. this sample is transferred to the receive filter. receive filter the receive section of the filter provides pass-band flatness and stop-band rejection that fulfills both the at&t d3/d4 specification and ccitt recommendation g.712. the filter contains the required compensation for the (sin x)/x response of such decoders.
tcm29c13a, tcm29c14a, tcm29c16a, tcm29c17a, tcm129c13a, tc,129c14a, tcm129c16a, tcm129c17a combined single-chip pcm codec and filter scts030e august 1989 revised october 1996 24 post office box 655303 ? dallas, texas 75265 principles of operation receive output power amplifiers a balanced-output amplifier allows maximum flexibility in output configuration. either of the two outputs can be used single ended (i.e., referenced to anlg gnd) to drive single-ended loads. alternatively, the differential output directly drives a bridged load. the output stage is capable of driving loads as low as 300- w single-ended to a level of 12 dbm or 600 w differentially to a level of 15 dbm. the receive channel transmission level may be adjusted between specified limits by manipulation of gsr. gsr is internally connected to an analog gain-setting network. when gsr is connected to pwro , the receive level is maximum. when gsr is connected to pwro+, the level is minimum. the output transmission level is adjusted between 0 and 12 db as gsr is adjusted (with an adjustable resistor) between pwro+ and pwro . transmission levels are specified relative to the receive channel output under digital milliwatt conditions (i.e., when the digital input at pcm in is the eight-code sequence specified in ccitt recommendation g.711). application information output gain-set design considerations (see figure 9) pwro+ and pwro are low-impedance complementary outputs. the voltages at the nodes are: v o+ at pwro + v o at pwro v o = v o+ v o (total differential response) r1 and r2 are a gain-setting resistor network with the center tap connected to the gsr input. a value greater than 10 k w and less than 100 k w for r1 + r2 is recommended because of the following: the parallel combination of r1 + r2 and r l sets the total loading. the total capacitance at the gsr input and the parallel combination of r1 and r2 define a time constant that has to be minimized to avoid inaccuracies. v a represents the maximum available digital milliwatt output response (v a = 3.006 vrms). v od = a ? v a where a = 1 + (r1/r2) 4 + (r1/r2) pwro+ gsr pwro 2 4 3 r1 r2 v od v o r l pcm in tcm29c13a tcm29c14a tcm29c16a tcm29c17a tcm129c13a tcm129c14a tcm129c16a tcm129c17a v o digital milliwatt sequence per ccitt g. 711 figure 10. gain-setting configuration
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated

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